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March 2007
HYB25D256[40/80/16]0CE(L) HYB25D256[40/80/16]0C[T/C/F] HYI25D256[80/16]0C[C/E/F/T]
256-Mbit Double-Data-Rate SDRAM DDR SDRAM RoHS Compliant or Lead-Containing
Internet Data Sheet
Rev. 2.3
Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
HYB25D256[40/80/16]0CE(L), HYB25D256[40/80/16]0C[T/C/F], HYI25D256[80/16]0C[C/E/F/T] Revision History: 2007-03, Rev. 2.3 Page All 17 72 85, 86 Subjects (major changes since last revision) Adapted internet edition Corrected table 7 mode register definition Changed the 1.1 mA to 1.5 mA for low power Changed the ball size from 0.460 mm to 0.450 mm
Previous Revision: 2007-01, Rev. 2.2
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07 03062006-8CCM-VPUW
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
1
1.1
Overview
Features
* * * * * * * * * * * Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes RAS-lockout supported tRAP = tRCD 7.8 s Maximum Average Periodic Refresh Interval 2.5 V (SSTL_2 compatible) I/O VDDQ = 2.5 V 0.2 V (DDR200, DDR266, DDR333); VDDQ = 2.6 V 0.1 V (DDR400) VDD = 2.5 V 0.2 V (DDR200, DDR266, DDR333); VDD = 2.6 V 0.1 V (DDR400) Standard Temperature Range (0 C - +70 C) or Industrial Temperature Range (-40 C - +85 C) P-TFBGA-60-12 package with 3 depopulated rows (8 x 12 mm2) P-TSOPII-66 package RoHS1) compliant product types available (green product)
This chapter lists all main features of the product family HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) and the ordering information.
* Double data rate architecture: two data transfers per clock cycle * Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver * DQS is edge-aligned with data for reads and is centeraligned with data for writes * Differential clock inputs (CK and CK) * Four internal banks for concurrent operation * Data mask (DM) for write data * DLL aligns DQ and DQS transitions with CK transitions * Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS * Burst Lengths: 2, 4, or 8 * CAS Latency: 1.5 (DDR200 only), 2, 2.5, 3
TABLE 1
Performance of -5, -6 and -7
Product Type Speed Code Speed Grade Max. Clock Frequency Component @CL3 @CL2.5 @CL2 -5 DDR400B -6 DDR333B 166 166 133 -7 DDR266A -- 143 133 Unit -- MHz MHz MHz
fCK3 fCK2.5 fCK2
200 166 133
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury, lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
1.2
Description
DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed. The address bits registered coincident with the Read or Write command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable Read or Write burst lengths of 2, 4 or 8 locations. An Auto Precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided along with a power-saving power-down mode. All inputs are compatible with SSTL_2. All outputs are SSTL_2, Class II compatible. Note: The functionality described and the timing specifications included in this data sheet are for the DLL Enabled mode of operation.
The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. The 256 Mbit Double-Data-Rate SDRAM uses a doubledata-rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256 Mbit Double-Data-Rate SDRAM effectively consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during Reads and by the memory controller during Writes. DQS is edge-aligned with data for Reads and center-aligned with data for Writes. The 256 Mbit Double-Data-Rate SDRAM operates from a differential clock (CK and CK; the crossing of CK going HIGH and CK going LOW is referred to as the positive edge of CK). Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 2
Ordering Information for Lead-Free Products (RoHS Compliant)
Product Type1) Organization CAS-RCD-RP Latencies 2.5-3-3 3-3-3 2.5-3-3 Clock (MHz) Speed Package Note
Standard Temperature Range (0 C - +70 C) HYB25D256800CE-5A x8 HYB25D256160CE-5A x16 HYB25D256800CE-5 HYB25D256160CE-5 HYB25D256800CE-6 HYB25D256160CE-6 HYB25D256400CE-7 HYB25D256400CF-5 HYB25D256800CF-5 HYB25D256160CF-5 HYB25D256400CF-6 HYB25D256800CF-6 HYB25D256160CF-6 HYI25D256800CE-5 HYI25D256160CE-5 HYI25D256800CE-6 HYI25D256160CE-6 HYI25D256800CF-5 HYI25D256160CF-5 HYI25D256800CF-6 HYI25D256160CF-6 x8 x16 x8 x16 x4 x4 x8 x16 x4 x8 x16 x8 x16 x8 x16 x8 x16 x8 x16 2.5-3-3 166 DDR333 3-3-3 200 DDR400A PG-TFBGA-60 2.5-3-3 166 DDR333 3-3-3 200 DDR400B PG-TSOPII-66 2.5-3-3 166 DDR333 3-3-3 143 200 DDR266A DDR400A PG-TFBGA-60 166 DDR333 200 DDR400B 200 DDR400A PG-TSOPII-66
HYB25D256800CEL-6 x8 HYB25D256160CEL-6 x16
Industrial Temperature Range (-40 C - +85 C)
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 3
Ordering Information for Lead-Containing Products
Product Type1) Oganization CAS-RCD-RP Clock (MHz) Speed Latencies x4 x8 x16 x4 x8 x16 x4 x4 x8 x16 x4 x8 x16 x8 x16 x8 x16 x8 x16 x8 x16 2.5-3-3 166 DDR333 3-3-3 200 DDR400A P-TFBGA-60 2.5-3-3 166 DDR333 3-3-3 200 DDR400B P-TSOPII-66 -- 2.5-3-3 166 DDR333 3-3-3 143 200 DDR266A DDR400B P-TFBGA-60 2.5-3-3 166 DDR333 3-3-3 200 Package Note
Standard Temperature Range (0 C - +70 C) HYB25D256400CT-5 HYB25D256800CT-5 HYB25D256160CT-5 HYB25D256400CT-6 HYB25D256800CT-6 HYB25D256160CT-6 HYB25D256400CT-7 HYB25D256400CC-5 HYB25D256800CC-5 HYB25D256160CC-5 HYB25D256400CC-6 HYB25D256800CC-6 HYB25D256160CC-6 HYI25D256800CT-5 HYI25D256160CT-5 HYI25D256800CT-6 HYI25D256160CT-6 HYI25D256800CC-5 HYI25D256160CC-5 HYI25D256800CC-6 HYI25D256160CC-6 DDR400B P-TSOPII-66 --
HYB25D256800CTL-6 x8
Industrial Temperature Range (-40 C - +85 C)
1) HYB and HYI: designator for memory components; 25D: DDR SDRAMs at VDDQ = 2.5 V; 256: 256-Mbit density; 400/800/160: product variations x4, x8 and x16; C: die revision C; L: low power (available on request); F/C/E/T: package type FBGA (lead & halogen free), FBGA (lead containing), TSOP (lead & halogen free), and TSOP (lead containing)
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
2
Pin Configuration
The pin configuration of a DDR SDRAM is listed by function in Table 4 (60 pins). The abbreviations used in the Pin#/Buffer# column are explained in Table 5 and Table 6 respectively. The pin numbering for FBGA is depicted in Figure 1 and that of the TSOP package in Figure 2.
TABLE 4
Pin Configuration of DDR SDRAM
Ball#/Pin# Clock Signals G2, 45 G3, 46 H3, 44 Control Signals H7, 23 G8, 22 G7, 21 H8, 24 J8, 26 J7, 27 K7, 29 L8, 30 L7, 31 M8, 32 M2, 35 L3, 36 L2, 37 K3, 38 K2, 39 J3, 40 K8, 28 J2, 41 H2, 42 RAS CAS WE CS BA0 BA1 A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 AP A11 A12 NC F9, 17 A13 NC I I I I I I I I I I I I I I I I I I I I NC I NC SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL -- SSTL -- Address Signal 12 Note: 256 Mbit or larger dies Note: 128 Mbit or smaller dies Address Signal 13 Note: 1 Gbit based dies Note: 512 Mbit or smaller dies Address Bus 11:0 Row Address Strobe Column Address Strobe Write Enable Chip Select Bank Address Bus 2:0 CK CK CKE I I I SSTL SSTL SSTL Clock Signal Complementary Clock Signal Clock Enable Name Pin Type Buffer Type Function
Address Signals
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin Type I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
Buffer Type SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL SSTL
Function
Data Signals x4 Organization B7, 5 D7, 11 D3, 56 B3, 62 E3, 51 F3, 47 A8, 2 B7, 5 C7, 8 D7, 11 D3, 56 C3, 59 B3, 62 A2, 65 E3, 51 F3, 47 A8, 2 B9, 4 B7, 5 C9, 7 C7, 8 D9, 10 D7, 11 E9, 13 E1, 54 D3, 56 D1, 57 C3, 59 C1, 60 B3, 62 B1, 63 A2, 65 DQ0 DQ1 DQ2 DQ3 DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS DM DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 Data Signal 3:0
Data Strobe x4 Organisation Data Strobe Data Mask Data Signal 7:0 Data Mask x4 Organization Data Signals x8 organization
Data Signal
Data Strobe x8 organisation Data Strobe Data Mask Data Signal 15:0 Data Mask x8 organization Data Signals x16 organization
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
Ball#/Pin#
Name
Pin Type I/O I/O I I AI PWR
Buffer Type SSTL SSTL SSTL SSTL -- --
Function
Data Strobe x16 organization E3, 51 E7, 16 F3, 47 F7, 20 Power Supplies F1, 49 UDQS LDQS UDM LDM Data Strobe Upper Byte Data Strobe Lower Byte Data Mask Upper Byte Data Mask Lower Byte I/O Reference Voltage I/O Driver Power Supply
Data Mask x16 organization
VREF A9, B2, C8, D2, VDDQ
E8, 3, 9, 15, 55, 61 A7, F8, M7, 1, 18, 33
VDD
PWR PWR
-- --
Power Supply Power Supply
A1, B8, C2, D8, VSSQ E2, 6, 12, 52, 58, 64 A3, F2, M3, 34, VSS 48, 66 Not Connected A2, 65 A8, 2 B1, 63 B9, 4 C1, 60 C3, 59 C7, 8 C9, 7 D1, 57 D9, 10 E1, 54 NC NC NC NC NC NC NC NC NC NC NC
PWR
--
Power Supply
NC NC NC NC NC NC NC NC NC NC NC
-- -- -- -- -- -- -- -- -- -- --
Not Connected Note: x4 organization Not Connected Note: x4 organization Not Connected Note: x8 and x4 organisation Not Connected Note: x8 and x4 organization Not Connected Note: x8 and x4 organization Not Connected Note: x4 organization Not Connected Note: x4 organization Not Connected Note: x8 and x4 organization Not Connected Note: x8 and x4 organization Not Connected Note: x8 and x4 organization Not Connected Note: x8 and x4 organization
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
Ball#/Pin# E7, 16 E9, 13 F7, 20 F9, 14, 17, 19, 25,43, 50, 53
Name NC NC NC NC
Pin Type NC NC NC NC
Buffer Type -- -- -- --
Function Not Connected Note: x8 and x4 organization Not Connected Note: x8 and x4 organization Not Connected Note: x8 and x4 organization Not Connected Note: x16,x8 and x4 organization
TABLE 5
Abbreviations for Pin Type
Abbreviation I O I/O AI PWR GND NC Description Standard input-only pin. Digital levels. Output. Digital levels. I/O is a bidirectional input/output signal. Input. Analog levels. Power Ground Not Connected
TABLE 6
Abbreviations for Buffer Type
Abbreviation SSTL LV-CMOS CMOS OD Description Serial Stub Terminated Logic (SSTL2) Low Voltage CMOS CMOS Levels Open Drain. The corresponding pin has 2 operational states, active low and tristate, and allows multiple devices to share as a wire-OR.
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
FIGURE 1
Pin Configuration P-TFBGA-60 Top View, see the balls throught the package
9664 1& 1& 1& 1& 95() 1& 9''4 9664 9''4 9664 966 &. 966 '4 1& '4 '46 '0 &. $ % & ' ( ) * + . / 0 [ 9664 '4 '4 '4 '4 95() '4 9''4 9664 9''4 9664 966 &. 966 '4 '4 '4 8'46 8'0 &. $ % & ' ( ) * + . / 0 [ 9'' '4 '4 '4 /'46 /'0 :( 5$6 %$ $ $ 9'' '4 9664 9''4 9664 9''4 9'' &$6 &6 %$ $$3 $ $ 033' 9''4 '4 '4 '4 '4 1&$ 9'' '4 1& '4 1& 1& :( 5$6 %$ $ $ 9'' 1& 9664 9''4 9664 9''4 9'' &$6 &6 %$ $$3 $ $ 9''4 1& 1& 1& 1& 1&$ 9664 1& 1& 1& 1& 95() '4 9''4 9664 9''4 9664 966 &. 966 '4 '4 '4 '46 '0 &. $ % & ' ( ) * + . / 0 [ 9'' '4 '4 '4 1& 1& :( 5$6 %$ $ $ 9'' '4 9664 9''4 9664 9''4 9'' &$6 &6 %$ $$3 $ $ 9''4 1& 1& 1& 1& 1&$
1&,$ &.( $ $ $ $ $ $ $ 966
1&,$ &.( $ $ $ $ $ $ $ 966
1&,$ &.( $ $ $ $ $ $ $ 966
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
FIGURE 2
Pin Configuration P-TSOPII-66-1
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
3
Functional Description
The 256 Mbit Double-Data-Rate SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. The 256 Mbit Double-Data-Rate SDRAM is internally configured as a quad-bank DRAM. The 256 Mbit Double-Data-Rate SDRAM uses a double-data-rate architecture to achieve high-speed operation. The doubledata-rate architecture is essentially a 2n prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 256 Mbit Double-Data-Rate SDRAM consists of a single 2n-bit wide, one clock cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an Active command, which is then followed by a Read or Write command. The address bits registered coincident with the Active command are used to select the bank and row to be accessed (BA0, BA1 select the bank; A0-A12 select the row). The address bits registered coincident with the Read or Write command are used to select the starting column location for the burst access. Prior to normal operation, the DDR SDRAM must be initialized. The following sections provide detailed information covering device initialization, register definition, command descriptions and device operation.
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 7
Mode Register
Field BL Bits [2:0] Type1) W Description Burst Length Number of sequential bits per DQ related to one read/write command. Note: All other bit combinations are RESERVED. 001B 2 010B 4 011B 8 BT 3 Burst Type See Table 8 for internal address sequence of low order address bits. 0 Sequential 1 Interleaved CAS Latency Number of full clocks from read command to first data valid window. Note: All other bit combinations are RESERVED. 010B 011B 110B 101B Note: MODE [12:7] 2 3 2.5 1.5 DDR200 components only
CL
[6:4]
Operating Mode Note: All other bit combinations are RESERVED. 000000 Normal Operation without DLL Reset 000010 Normal Operation with DLL Reset
1) W = write only register bit
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 8
Burst Definition
Burst Length Starting Column Address A2 2 4 -- -- -- -- -- -- 8 0 0 0 0 1 1 1 1 Notes 1. 2. 3. 4. For a burst length of two, A1-Ai selects the two-data-element block; A0 selects the first access within the block. For a burst length of four, A2-Ai selects the four-data-element block; A0-A1 selects the first access within the block. For a burst length of eight, A3-Ai selects the eight-data- element block; A0-A2 selects the first access within the block. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. A1 -- -- 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Order of Accesses Within a Burst Type = Sequential 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 Type = Interleaved 0-1 1-0 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 9
Extended Mode Regsiter
Field DLL Bits 0 Type1) W Description DLL Status 0B Enabled Disabled 1B Drive Strength 0B Normal 1B Weak Operating Mode Note: All other bit combinations are RESERVED. 00000000000BNormal Operation
1) W = write only register bit
DS
1
W
MODE
[12:2]
W
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 10
Truth Table 1a: Commands
Name (Function) Deselect (NOP) No Operation (NOP) Active (Select Bank And Activate Row) Read (Select Bank And Column, And Start Read Burst) Write (Select Bank And Column, And Start Write Burst) Burst Terminate Precharge (Deactivate Row In Bank Or Banks) Auto Refresh Or Self Refresh (Enter Self Refresh Mode) Mode Register Set
1) 2) 3) 4) 5) 6) 7) 8) 9)
CS H L L L L L L L L
RAS X H L H H H L L L
CAS X H H L L H H L L
WE X H H H L L L H L
Address X X Bank/Row Bank/Col Bank/Col X Code X Op-Code
MNE NOP NOP ACT Read Write BST PRE AR/SR MRS
Note
1)2) 1)2) 1)3) 1)4) 1)4) 1)5) 1)6) 1)7)8) 1)9)
CKE is HIGH for all commands shown except Self Refresh.VREF must be maintained during Self Refresh operation Deselect and NOP are functionally interchangeable. BA0-BA1 provide bank address and A0-A12 provide row address. BA0, BA1 provide bank address; A0-Ai provide column address (where i = 8 for x16, i = 9 for x8 and 9, 11 for x4); A10 HIGH enables the Auto Precharge feature (nonpersistent), A10 LOW disables the Auto Precharge feature. Applies only to read bursts with Auto Precharge disabled; this command is undefined (and should not be used) for read bursts with Auto Precharge enabled or for write bursts. A10 LOW: BA0, BA1 determine which bank is precharged. A10 HIGH: all banks are precharged and BA0, BA1 are "Don't Care". This command is Auto Refresh if CKE is HIGH; Self Refresh if CKE is LOW. Internal refresh counter controls row and bank addressing; all inputs and I/Os are "Don't Care" except for CKE. BA0, BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are reserved; A0-A12 provide the op-code to be written to the selected Mode Register).
TABLE 11
Truth Table 1b: DM Operation
Name (Function) Write Enable Write Inhibit
1) Used to mask write data; provided coincident with the corresponding data.
DM L H
DQs Valid X
Note
1) 1)
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 12
Truth Table 2: Clock Enable (CKE)
Current State CKE n-1 Previous Cycle Self Refresh Self Refresh Power Down Power Down All Banks Idle All Banks Idle Bank(s) Active -- L L L L H H H H CKEn Current Cycle L H L H L L L H X Deselect or NOP X Deselect or NOP Deselect or NOP AUTO REFRESH Deselect or NOP See Table 13 Maintain Self-Refresh Exit Self-Refresh Maintain Power-Down Exit Power-Down Precharge Power-Down Entry Self Refresh Entry Active Power-Down Entry --
1) 2)
Command n
Action n
Note
1) VREF must be maintained during Self Refresh operation 2) Deselect or NOP commands should be issued on any clock edges occurring during the Self Refresh Exit (tXSNR) period. A minimum of 200 clock cycles are needed before applying a read command to allow the DLL to lock to the input clock.
Notes 1. 2. 3. 4. CKEn is the logic state of CKE at clock edge n: CKE n-1 was the state of CKE at the previous clock edge. Current state is the state of the DDR SDRAM immediately prior to clock edge n. COMMAND n is the command registered at clock edge n, and ACTION n is a result of COMMAND n. All states and sequences not shown are illegal or reserved.
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 13
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
Current State Any Idle CS H L L L L Row Active L L L Read (Auto Precharge Disabled) Write (Auto Precharge Disabled) L L L L L L RAS X H L L L H H L H L H H H L CAS X H H L L L L H L H H L L H WE X H H H L H L L H L L H L L Command Deselect No Operation Active AUTO REFRESH MODE REGISTER SET Read Write Precharge Read Precharge BURST TERMINATE Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. Select and activate row -- -- Select column and start Read burst Select column and start Write burst Deactivate row in bank(s) Select column and start new Read burst Truncate Read burst, start Precharge BURST TERMINATE Select column and start Read burst Select column and start Write burst Note
1)2)3)4)5)6) 1) to 6) 1) to 6) 1) to7) 1) to 7)
1) to 6),8) 1) to 6),8) 1) to 6),9) 1) to 6),8) 1) to 6),9) 1) to 6),10)
1) to 6), 8),11) 1) to 6),8)
was self refresh). 2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed to be issued to that bank when in that state. Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. 4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge command and ends when tRP is met. Once tRP is met, the bank is in the idle state. Row Activating: Starts with registration of an Active command and ends when tRCD is met. Once tRCD is met, the bank is in the "row active" state. Read w/Auto Precharge Enabled: Starts with registration of a Read command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when tRP has been met. Once tRP is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and according to Table 14. 5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when tRFC is met. Once tRFC is met, the DDR SDRAM is in the "all banks idle" state. Accessing Mode Register: Starts with registration of a Mode Register Set command and ends when tMRD has been met. Once tMRD is met, the DDR SDRAM is in the "all banks idle" state. Precharging All: Starts with registration of a Precharge All command and ends when tRP is met. Once tRP is met, all banks is in the idle state. 6) All states and sequences not shown are illegal or reserved. 7) Not bank-specific; requires that all banks are idle. 8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging. 10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank. 11) Requires appropriate DM masking.
1) to 6),9),11) Truncate Write burst, start Precharge 1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12 and after tXSNR/tXSRD has been met (if the previous state
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TABLE 14
Truth Table 4: Current State Bank n - Command to Bank m (different bank)
Current State Any Idle CS H L X RAS CAS WE X H X X H X X H X Command Deselect No Operation Any Command Otherwise Allowed to Bank m Active Read Write Precharge Active Read Precharge Active Read Write Precharge Active Read Write Precharge Active Read Write Precharge Action NOP. Continue previous operation. NOP. Continue previous operation. -- Note
1)2)3)4)5)6) 1) to 6) 1) to 6)
Row Activating, Active, or Precharging
L L L L L L L L L L L
L H H L L H L L H H L L H H L L H H L
H L L H H L H H L L H H L L H H L L H
H H L L H H L H H L L H H L L H H L L
Select and activate row Select column and start Read burst Select column and start Write burst -- Select and activate row Select column and start new Read burst -- Select and activate row Select column and start Read burst Select column and start new Write burst -- Select and activate row Select column and start new Read burst Select column and start Write burst -- Select and activate row Select column and start Read burst Select column and start new Write burst --
1) to 6) 1) to7) 1) to 7) 1) to 6) 1) to 6) 1) to 7) 1) to 6) 1) to 6) 1) to8) 1) to 7) 1) to 6) 1) to 6) 1) to 7),9) 1) to 7),9),10) 1) to 6) 1) to 6) 1) to 7),9) 1) to 7),9) 1) to 6)
Read (Auto Precharge Disabled) Write (Auto Precharge Disabled)
Read (With Auto Precharge)
L L L L
Write (With Auto Precharge)
L L L L
1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see Table 12: Clock Enable (CKE) and after tXSNR/tXSRD has been met (if the previous state was self refresh). 2) This table describes alternate bank operation, except where noted, i.e., the current state is for bank n and the commands shown are those allowed to be issued to bank m (assuming that bank m is in such a state that the given command is allowable). Exceptions are covered in the notes below. 3) Current state definitions: Idle: The bank has been precharged, and tRP has been met. Row Active: A row in the bank has been activated, and tRCD has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge disabled, and has not yet terminated or been terminated. Read with Auto Precharge Enabled: See 10). Write with Auto Precharge Enabled: See 10). 4) AUTO REFRESH and Mode Register Set commands may only be issued when all banks are idle. 5) A BURST TERMINATE command cannot be issued to another bank; it applies to the bank represented by the current state only. 6) All states and sequences not shown are illegal or reserved. 7) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with Auto Precharge disabled. 8) Requires appropriate DM masking.
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9) Concurrent Auto Precharge: This device supports "Concurrent Auto Precharge". When a read with auto precharge or a write with auto precharge is enabled any command may follow to the other banks as long as that command does not interrupt the read or write data transfer and all other limitations apply (e.g. contention between READ data and WRITE data must be avoided). The minimum delay from a read or write command with auto precharge enable, to a command to a different banks is summarized in Table 15. 10) A Write command may be applied after the completion of data output.
TABLE 15
Truth Table 5: Concurrent Auto Precharge
From Command WRITE w/AP To Command (different bank) Read or Read w/AP Write to Write w/AP Precharge or Activate Read w/AP Read or Read w/AP Write or Write w/AP Precharge or Activate Minimum Delay with Concurrent Auto Unit Precharge Support 1 + (BL/2) + tWTR BL/2 1 BL/2 CL (rounded up) + BL/2 1
tCK tCK tCK tCK tCK tCK
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4
4.1
Electrical Characteristics
Operating Conditions
TABLE 16
Absolute Maximum Ratings
This chapter lists the electrical characteristics.
This chapter contains the operating conditions tables.
Parameter
Symbol Min.
Values Typ. -- -- -- -- -- -- -- -- 1 50 Max.
Unit
Note/ Test Condition
Voltage on I/O pins relative to VSS Voltage on inputs relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Operating temperature (ambient)
VIN, VOUT VIN VDD VDDQ TA
-0.5 -1 -1 -1 0 -40 -25
VDDQ + 0.5
+3.6 +3.6 +3.6 +70 +85 +85 +150 -- --
V V V V C C C C W mA HYB HYI HYE
Storage temperature (plastic) Power dissipation (per SDRAM component) Short circuit output current
TSTG PD IOUT
-55 -- --
Attention: Stresses above the max. values listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit.
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TABLE 17
Input and Output Capacitances
Parameter Symbol Min. Input Capacitance: CK, CK Delta Input Capacitance Input Capacitance: All other input-only pins Delta Input Capacitance: All other input-only pins Input/Output Capacitance: DQ, DQS, DM Values Typ. -- -- -- -- -- -- -- -- -- Max. 2.5 3.0 0.25 2.5 3.0 0.5 4.5 5.0 0.5 pF pF pF pF pF pF pF pF pF Unit Note/ Test Condition P-TFBGA-60-121) P-TSOPII-66 1)
1)
CI1 CdI1 CI2 CdIO CIO
1.5 2.0 -- 1.5 2.0 -- 3.5 4.0
P-TFBGA-60-12 1) P-TSOPII-66 1)
1)
P-TFBGA-60-12 P-TFBGA-60-12 1)2) P-TSOPII-66 1)2)
1)
Delta Input/Output Capacitance: DQ, DQS, DM
CdIO
--
1) These values are not subject to production test - verified by design/characterization and are tested on a sample base only. VDDQ = VDD = 2.5 V 0.2 V, f = 100 MHz, TA = 25 C, VOUT(DC) = VDDQ/2, VOUT (Peak to Peak) 0.2 V. Unused pins are tied to ground. 2) DM inputs are grouped with I/O pins reflecting the fact that they are matched in loading to DQ and DQS to facilitate trace matching at the board level.
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TABLE 18
Electrical Characteristics and DC Operating Conditions
Parameter Symbol Min. Device Supply Voltage Device Supply Voltage Output Supply Voltage Output Supply Voltage Supply Voltage, I/O Supply Voltage Input Reference Voltage I/O Termination Voltage (System) Input High (Logic1) Voltage Values Typ. 2.5 2.6 2.5 2.6 -- 0.5 x VDDQ -- -- -- -- -- -- -- -- -- Max. 2.7 2.7 2.7 2.7 0 0.51 x VDDQ VREF + 0.04 VDDQ + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.4 2 5 -16.2 -- V V V V V V V V V V V -- A A mA mA
4) 5)
Unit Note/Test Condition1)
VDD VDD VDDQ VDDQ VSS, VSSQ VREF VTT
2.3 2.5 2.3 2.5 0 0.49 x VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 0.71 -2 -5 --
fCK 166 MHz fCK > 166 MHz2) fCK 166 MHz3) fCK > 166 MHz 2)3)
VIH(DC) Input Low (Logic0) Voltage VIL(DC) Input Voltage Level, CK and VIN(DC)
CK Inputs Input Differential Voltage, CK and CK Inputs VI-Matching Pull-up Current to Pull-down Current Input Leakage Current Output Leakage Current
6) 6) 6)
VID(DC) VRatio II IOZ
6)7)
8)
Any input 0 V VIN VDD; All other pins not under test = 0 V9) DQs are disabled; 0 V VOUT VDDQ 9) VOUT = 1.95 V VOUT = 0.35 V
Output High Current, Normal IOH Strength Driver
Output Low Current, Normal IOL 16.2 -- Strength Driver 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V;
2) 3) 4) 5) 6) 7) 8)
9)
DDR400 conditions apply for all clock frequencies above 166 MHz Under all conditions, VDDQ must be less than or equal to VDD. Peak to peak AC noise on VREF may not exceed 2% VREF.DC. VREF is also expected to track noise variations in VDDQ. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The ratio of the pull-up current to the pull-down current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltage from 0.25 to 1.0 V. For a given output, it represents the maximum difference between pull-up and pull-down drivers due to process variation. Values are shown per pin.
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4.2
AC Characteristics
(Notes 1-5 apply to the following Tables; Electrical Characteristics and DC Operating Conditions, AC Operating Conditions, IDD Specifications and Conditions, and Electrical Characteristics and AC Timing.) Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical, AC and DC characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 3 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK, CK), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e. the receiver effectively switches as a result of the signal crossing the AC input level, and remains in that state as long as the signal does not ring back above (below) the DC input LOW (HIGH) level). 6. For System Characteristics like Setup & Holdtime Derating for Slew Rate, I/O Delta Rise/Fall Derating, DDR SDRAM Slew Rate Standards, Overshoot & Undershoot specification and Clamp V-I characteristics see the latest JEDEC specification for DDR components.
FIGURE 3
AC Output Load Circuit Diagram / Timing Reference Load
VTT
50 Output (VOUT) Timing Reference Point 30 pF
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TABLE 19
AC Operating Conditions
Parameter Symbol Min. Input High (Logic 1) Voltage, DQ, DQS and DM Signals Input Low (Logic 0) Voltage, DQ, DQS and DM Signals Input Differential Voltage, CK and CK Inputs Input Closing Point Voltage, CK and CK Inputs Values Max. -- V V V Unit Note1)/ Test Condition
2)3) 2)3) 2)3)4)
2)3)5) 0.5 x VDDQ- V 0.2 0.2 1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR200 - DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400); 0 C TA 70 C
VIH(AC) VIL(AC) VID(AC) VIX(AC)
VREF + 0.31
-- 0.7
VREF - 0.31 VDDQ + 0.6 0.5 x VDDQ+
2) 3) 4) 5)
Input slew rate = 1 V/ns. Inputs are not recognized as valid until VREF stabilizes. VID is the magnitude of the difference between the input level on CK and the input level on CK. The value of VIX is expected to equal 0.5 x VDDQ of the transmitting device and must track variations in the DC level of the same.
TABLE 20
AC Timing - Absolute Specifications for PC3200 and PC2700
Parameter Symbol -5 DDR400B Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.5 0.55 8 12 12 0.55 -6 DDR333 Min. -0.7 0.45 6 6 7.5 0.45 Max. +0.7 0.55 12 12 12 0.55 ns
2)3)4)5)
Unit Note/ Test Condition1)
tAC tCH tCK
-0.5 0.45 5 6 7.5
tCK
ns ns ns
2)3)4)5)
CL = 3.0 3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle) DQS-DQ skew (DQS and associated DQ signals) Write command to 1st DQS latching transition DQ and DM input setup time
tCL tDAL tDH tDIPW tDQSCK tDQSL,H tDQSQ tDQSS tDS
0.45 (tWR/tCK)+(tRP/tCK) 0.4 1.75 -0.6 0.35 -- 0.72 0.4
tCK tCK
ns ns ns
-- -- +0.6 -- +0.40 1.25 --
0.45 1.75 -0.6 0.35 -- 0.75 0.45
-- -- +0.6 -- +0.40 1.25 --
2)3)4)5) 2)3)4)5)6)
2)3)4)5)
tCK
ns
2)3)4)5)
TFBGA 2)3)4)5)
2)3)4)5)
tCK
ns
2)3)4)5)
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Parameter
Symbol
-5 DDR400B Min. Max. -- -- -- +0.7 -- -- -- -- -- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 --
-6 DDR333 Min. 0.2 0.2 Min. (tCL, tCH) -0.7 0.75 0.8 2.2 0.75 0.8 -0.7 2 Max. -- -- -- +0.7 -- -- -- -- -- +0.7 -- -- +0.50 -- 70E+3 -- -- 7.8 -- -- 1.1 0.60 -- -- -- 0.60 --
Unit Note/ Test Condition1)
DQS falling edge hold time from CK (write cycle)
tDSH
0.2 0.2 Min. (tCL, tCH) -- 0.6 0.7
tCK tCK
ns ns ns ns ns ns ns ns
2)3)4)5)
DQS falling edge to CK setup time tDSS (write cycle) Clock Half Period Data-out high-impedance time from CK/CK Address and control input hold time
2)3)4)5)
tHP tHZ tIH
2)3)4)5) 2)3)4)5)7)
Fast slew rate
3)4)5)6)8)
Slow slew rate
3)4)5)6)8) 2)3)4)5)9)
Control and Addr. input pulse width (each input) Address and control input setup time
tIPW tIS
2.2 0.6 0.7
Fast slew rate
3)4)5)6)8)
Slow slew rate
3)4)5)6)8) 2)3)4)5)7)
Data-out low-impedance time from CK/CK
tLZ
-0.7 2
Mode register set command cycle tMRD time DQ/DQS output hold time Data hold skew factor Active to Autoprecharge delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay
tCK
ns ns ns ns ns ns s ns ns
2)3)4)5)
tQH tQHS tRAP tRAS tRC
tHP -tQHS
--
tHP -tQHS
--
2)3)4)5)
TFBGA 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5)
tRCD
40 55 15 -- 65 15 0.9 0.40 10 0.25 0 0.40 15
tRCD
42 60 18 -- 72 18 0.9 0.40 12 0.25 0 0.40 15
tRCD Average Periodic Refresh Interval tREFI Auto-refresh to Active/AutotRFC
refresh command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Precharge command period
2)3)4)5) 2)3)4)5)10) 2)3)4)5)
tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)
tCK tCK
ns
tCK
ns
2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5)
tCK
ns
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Parameter
Symbol
-5 DDR400B Min. Max. -- --
-6 DDR333 Min. 1 75 Max. -- --
Unit Note/ Test Condition1)
Internal write to read command delay Exit self-refresh to non-read command
tWTR tXSNR
2 75
tCK
ns
2)3)4)5)
2)3)4)5)
2) Input slew rate 1 V/ns for DDR400, DDR333 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual systemclock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 11) The specific requirement is that DQS be valid (HIGH,LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specificationsof the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly.
2)3)4)5) Exit self-refresh to read command tXSRD 200 -- 200 -- tCK 1) 0 C TA 70 C; VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V (DDR333); VDDQ = 2.6 V 0.1 V, VDD = +2.6 V 0.1 V (DDR400)
TABLE 21
AC Timing - Absolute Specifications for PC2700
Parameter Symbol -7 DDR266A Min. DQ output access time from CK/CK CK high-level width Clock cycle time Max. +0.75 0.55 12 12 12 0.55 -- -- -- +0.75 -- ns
2)3)4)5) 2)3)4)5)
Unit
Note/Test Condition1)
tAC tCH tCK
-0.75 0.45 7.5 7.5 7.5
tCK
ns ns ns
CL = 3.0 3)4)5) CL = 2.5 2)3)4)5) CL = 2.0 2)3)4)5)
2)3)4)5) 2)3)4)5)6) 2)3)4)5) 2)3)4)5)6) 2)3)4)5) 2)3)4)5)
CK low-level width Auto precharge write recovery + precharge time DQ and DM input hold time DQ and DM input pulse width (each input) DQS output access time from CK/CK DQS input low (high) pulse width (write cycle)
tCL tDAL tDH tDIPW tDQSCK tDQSL,H
0.45 (tWR/tCK)+(tRP/tCK) 0.5 1.75 -0.75 0.35
tCK tCK
ns ns ns
tCK
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Parameter
Symbol
-7 DDR266A Min. Max. +0.5 +0.5 1.25 -- -- -- -- +0.75 -- -- -- -- -- +0.75 -- -- 0.75 0.75 -- 120E+3 -- -- -- -- -- 1.1 0.6 -- -- -- -- -- --
Unit
Note/Test Condition1)
DQS-DQ skew (DQS and associated DQ signals) tDQSQ
-- -- 0.75 0.5 0.2 0.2 Min. (tCL, tCH) -0.75 0.9 1.0
ns ns
FBGA 2)3)4)5) TSOPII 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)7)
tDQSS DQ and DM input setup time tDS DQS falling edge hold time from CK (write cycle) tDSH DQS falling edge to CK setup time (write cycle) tDSS Clock Half Period tHP Data-out high-impedance time from CK/CK tHZ Address and control input hold time tIH
Write command to 1 DQS latching transition
st
tCK
ns
tCK tCK
ns ns ns ns ns ns ns ns
Fast slew rate
3)4)5)6)8)
Slow slew rate
3)4)5)6)8) 2)3)4)5)9)
Control and Addr. input pulse width (each input) Address and control input setup time
tIPW tIS
2.2 0.9 1.0
Fast slew rate
3)4)5)6)8)
Slow slew rate
3)4)5)6)8) 2)3)4)5)7) 2)3)4)5) 2)3)4)5)
Data-out low-impedance time from CK/CK Mode register set command cycle time DQ/DQS output hold time Data hold skew factor Active to Read w/AP delay Active to Precharge command Active to Active/Auto-refresh command period Active to Read or Write delay Average Periodic Refresh Interval Auto-refresh to Active/Auto-refresh command period Precharge command period Read preamble Read postamble Active bank A to Active bank B command Write preamble Write preamble setup time Write postamble Write recovery time Internal write to read command delay
tLZ tMRD tQH tQHS tRAP tRAS tRC tRCD tREFI tRFC tRP tRPRE tRPST tRRD tWPRE tWPRES tWPST tWR tWTR
-0.75 2
tCK
ns ns ns ns ns ns ns s ns ns
tHP - tQHS
-- --
FBGA 2)3)4)5) TSOPII 2)3)4)5)
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)10) 2)3)4)5)
tRCD
45 65 20 7.8 75 20 0.9 0.4 15 0.25 0 0.4 15 1
2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5) 2)3)4)5)11) 2)3)4)5)12) 2)3)4)5) 2)3)4)5)
tCK tCK
ns
tCK
ns
tCK
ns
tCK
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
Parameter
Symbol
-7 DDR266A Min. Max. -- --
Unit
Note/Test Condition1)
Exit self-refresh to non-read command
2) Input slew rate 1 V/ns 3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals other than CK/CK, is VREF. CK/CK slew rate are 1.0 V/ns. 4) Inputs are not recognized as valid until VREF stabilizes. 5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is VTT. 6) For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock cycle time. 7) tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ). 8) Fast slew rate 1.0 V/ns , slow slew rate 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured between VIH(ac) and VIL(ac). 9) These parameters guarantee device timing, but they are not necessarily tested on each device. 10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device. 11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system performance (bus turnaround) degrades accordingly. 13) In all circumstances, tXSNR can be satisfied using tXSNR = tRFC,min + 1 x tCK
Exit self-refresh to read command 1) VDDQ = 2.5 V 0.2 V, VDD = +2.5 V 0.2 V ; 0 C TA 70 C
tXSNR tXSRD
75 200
ns
2)3)4)5)13) 2)3)4)5)
tCK
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 22
IDD Conditions
Parameter Operating Current: one bank; active/ precharge; tRC = tRCMIN; tCK = tCKMIN; DQ, DM, and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. Operating Current: one bank; active/read/precharge; Burst = 4; Refer to the following page for detailed test conditions. Precharge Power-Down Standby Current: all banks idle; power-down mode; CKE VILMAX; tCK = tCKMIN Symbol
IDD0
IDD1 IDD2P
Precharge Floating Standby Current: CS VIHMIN, all banks idle; IDD2F CKE VIHMIN; tCK = tCKMIN, address and other control inputs changing once per clock cycle, VIN = VREF for DQ, DQS and DM. Precharge Quiet Standby Current:CS VIHMIN, all banks idle; CKE VIHMIN; tCK = tCKMIN, address and other control inputs stable at VIHMIN or VILMAX; VIN = VREF for DQ, DQS and DM. Active Power-Down Standby Current: one bank active; power-down mode; CKE VILMAX; tCK = tCKMIN; VIN = VREF for DQ, DQS and DM.
IDD2Q IDD3P
Active Standby Current: one bank active; CS VIHMIN; CKE VIHMIN; tRC = tRASMAX; tCK = tCKMIN; DQ, DM and DQS IDD3N inputs changing twice per clock cycle; address and control inputs changing once per clock cycle. Operating Current: one bank active; Burst = 2; reads; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN; IOUT = 0 mA Operating Current: one bank active; Burst = 2; writes; continuous burst; address and control inputs changing once per clock cycle; 50 % of data outputs changing on every clock edge; CL = 2 for DDR200 and DDR266A, CL = 3 for DDR333; tCK = tCKMIN Auto-Refresh Current: tRC = tRFCMIN, burst refresh Self-Refresh Current: CKE 0.2 V; external clock on; tCK = tCKMIN Operating Current: four bank; four bank interleaving with BL = 4; Refer to the following page for detailed test conditions.
IDD4R
IDD4W
IDD5 IDD6 IDD7
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
TABLE 23
IDD Specification
Symbol -5 DDR400B Typ. Max. 90 90 100 110 5 36 28 18 45 54 100 120 105 130 190 3.0 -- 250 250 -6 DDR333 Typ. 60 65 70 80 4 25 17 11 32 36 70 85 75 90 120 1.4 -- 180 180 Max. 75 75 85 95 5 30 24 15 38 45 85 100 90 110 160 3.0 1.5 215 -7 DDR266A Typ. 50 55 65 70 3 20 15 9 28 30 60 70 65 75 100 1.4 -- 140 Max. 65 65 75 85 4 24 21 13 36 40 70 85 75 90 140 3.0 -- 170 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA x4/x82)3) x16 3) x4/x8 3) x16 3)
3) 3) 3) 3) 3)
Unit
Note/Test Condition1)
IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 IDD7
70 75 80 95 4 30 20 13 38 43 85 100 90 100 140 1.4 -- 210 210
x16 3) x4/x8 3) x16 3) x4/x8 3) x16 3)
3) 4)
Low power5) x4/x8 3)
200 MHz for DDR400. 3) Input slew rate = 1 V/ns. 4) Enables on-chip refresh and address counters. 5) Low power available on request
215 140 170 mA x16 3) 1) Test conditions for typical values: VDD = 2.5 V (DDR333), VDD = 2.6 V (DDR400), TA = 25 C, test conditions for maximum values: VDD = 2.7 V, TA = 10 C 2) IDD specifications are tested after the device is properly initialized and measured at 133 MHz for DDR266, 166 MHz for DDR333, and
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
5
Package Outlines
There are two package types used for this product family each in lead-free and lead-containing assembly: * P-TFBGA: Plastic Thin Fine-Pitch Ball Grid Array Package
TABLE 24
TFBGA Common Package Properties (non-green/green)
Description Ball Size Recommended Landing Pad Recommended Solder Mask Size 0.450 0.500 0.400 Units mm mm mm
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
FIGURE 4
Package Outline of P-TFBGA-60-12 (non-green/green)
* P(G)-TFBGA-60: Plastic (non-green/green) Thin Fine Ball Grid Array
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
FIGURE 5
Package Outline of P-TSOPII-66-1 (non-green/green)
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Internet Data Sheet
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
List of Figures
Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Pin Configuration P-TFBGA-60 Top View, see the balls throught the package . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration P-TSOPII-66-1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Output Load Circuit Diagram / Timing Reference Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline of P-TFBGA-60-12 (non-green/green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline of P-TSOPII-66-1 (non-green/green). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 12 25 34 35
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
List of Tables
Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Table 10 Table 11 Table 12 Table 13 Table 14 Table 15 Table 16 Table 17 Table 18 Table 19 Table 20 Table 21 Table 22 Table 23 Table 24 Performance of -5, -6 and -7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Ordering Information for Lead-Free Products (RoHS Compliant). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Ordering Information for Lead-Containing Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin Configuration of DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Abbreviations for Pin Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Abbreviations for Buffer Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Mode Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Burst Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Extended Mode Regsiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Truth Table 1a: Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Truth Table 1b: DM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Truth Table 2: Clock Enable (CKE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Truth Table 3: Current State Bank n - Command to Bank n (same bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Truth Table 4: Current State Bank n - Command to Bank m (different bank). . . . . . . . . . . . . . . . . . . . . . . . . . 20 Truth Table 5: Concurrent Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Electrical Characteristics and DC Operating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC Timing - Absolute Specifications for PC3200 and PC2700. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AC Timing - Absolute Specifications for PC2700 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 IDD Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 IDD Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 TFBGA Common Package Properties (non-green/green) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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HY[B/I]25D256[16/40/80]0C[E/C/F/T](L) 256 Mbit Double-Data-Rate SDRAM
Table of Contents
1 1.1 1.2 2 3 4 4.1 4.2 5 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
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Internet Data Sheet
Edition 2007-03 Published by Qimonda AG Gustav-Heinemann-Ring 212 D-81739 Munchen, Germany (c) Qimonda AG 2007. All Rights Reserved. Legal Disclaimer The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics ("Beschaffenheitsgarantie"). With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office. Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Qimonda Office. Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. www.qimonda.com

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